Doing Verification Better! If VHDL is so good, why do we need UVM?
2022-26-1173
05/26/2022
- Event
- Content
- In today’s world, complex electronic systems demand integration of an increasing number of functionalities in the form of various IP cores into a single chip or System-On-Chip (SOC). System-level functional verification of such massive SOCs is also increasingly becoming more complex. As design engineers create more functionally dense chips, the functional verification methodology is parallelly advancing to provide modern techniques resulting in independent, scalable, and reusable verification IP components. Modern-day SOCs strongly require verification architectures with extended reusability and easier accessibility. This paper highlights the pros and cons of shifting from legacy test-bench modeling strategies to more scalable, reusable, and efficient methodologies. Conventional methodology does not support features like randomization, factory registration, callbacks, configuration database etc., without which thorough verification seems difficult. The aim of the paper is to portray the advantages of these features by applying UVM concepts, using the examples of peripheral bus protocols i.e. Serial Peripheral Interface (SPI) and Inter-Integrated Circuit (I2C). SPI and I2C are important as they are often used for both inter-chip and intra-chip communication in SOCs. Assessment metrics used to evaluate the pros and cons are based on the functional and code coverage achieved, code reusability, and stimuli generation. Conclusion: This paper demonstrated that it is possible to build a testbench that bends rather than breaks: one that adapts to multiple design versions and changes in hierarchy, can simulate subsystems in isolation, and achieves error-proof connectivity to the DUT.
- Citation
- Dwivedi, N., and Mookim, S., "Doing Verification Better! If VHDL is so good, why do we need UVM? ," SAE Technical Paper 2022-26-1173, 2022, .