Forging a cost-effective way of verifying devices with Analog inputs in UVM based environment
2022-26-1181
05/26/2022
- Event
- Content
- Safety is of utmost importance in the aerospace industry. Hence, verification of SOCs, subsystems and IPs used in the industry should be verified with latest methodology available in the market to deliver an optimal design. Some avionics systems are made up of components with analog inputs such as temperature sensor. These sensors are used in different parts of aircrafts such as Engine Fuel, Cabin temperature control, compressor discharge and many more. Thus, it is very important to verify them thoroughly. This paper talks about a simple technique which generates analog signals and enables such components to be verified in an UVM based verification environment. This can be achieved by creating a small model which generates a debouncing effect. Once the debounced signal is introduced, the devices can be verified thoroughly with the help of UVM testbench. The primary benefit is that the UVM methodology specifies and lays out a set of guidelines to be followed for creation of verification testbenches. Advantages of using this approach is that it is cost efficient as it does not require any tool to create the analog inputs. Also, it allows small devices with analog input to be verified in a robust verification methodology such as UVM. Conclusion: This paper highlights on how UVM methodology can be used to verify the Analog devices. Also, focuses on creation of simple models which can mimic the behavior of Analog signal instead of investing in expensive tools.
- Citation
- Harkude, A., "Forging a cost-effective way of verifying devices with Analog inputs in UVM based environment," SAE Technical Paper 2022-26-1181, 2022, .