A vertically reusable Testbench development guidelines and anonymous heroes of the ASIC/FPGA design verification process.
2022-26-1206
05/26/2022
- Content
- Developing a vertically reusable UVC is complex, having a uniform guideline helps convergence across the team and the project. An experienced user is also overwhelmed in an elaborate test bench if the Sub-system and System level test bench has multiple instances of the same UVC configured differently. Integrating a UVM UVC with weak architecture into the Subsystem or System level test bench can at best lead to integration and scalability issues, and in the worst-case scenario, it may result in re-usability issues causing rework. This paper discusses the standard UVC architecture and reactive slave agent architecture, implementation, and benefits in detail. The slave UVC is referred to as reactive or as a responder if Design under test or master drives the bus interface and slave UVC generates the response based on the observed request. The paper defines the UVM UVC development guidelines and architecture on using multiple instances of the same UVC and sequence reuse. It also draws attention to the typically left-out verification infrastructure such as UVC debug interface, Scoreboard Transaction Tracker, DUT Test Harness, Interrupt Framework, Macro Utilities, customized message logging, and formatting via report server class. Conclusion: This paper discusses the common problems with vertical reuse of UVC(s) and the approach used at Boeing to solve the same. In addition to that, this paper also draws attention to the forgotten heroes i.e. techniques and tricks used to improve the quality of verification and test bench infrastructure. *UVM - Universal verification methodology. *UVC - Universal Verification Component.
- Citation
- Yadav, M., "A vertically reusable Testbench development guidelines and anonymous heroes of the ASIC/FPGA design verification process.," SAE Technical Paper 2022-26-1206, 2022, .