Reducing Power-On/Off Glitches in Precision DACs: Part 2

introduced a phenomenon called power-on/off glitch. The example discussed the impact of this phenomenon on a motor control system. We limited our analysis to a DAC where the output buffer is powered on in normal mode: zero-scale or mid-scale. In Part 2, we analyze when the DAC output is powered on in high-impedance mode. We present a mathematical model for the power-on glitch, followed by board-level solutions to minimize it.