Miller-Jogging for Synthesizer Lock Algorithm Extension

The University of California Los Angeles (UCLA) has developed a wide range of CMOS (complementary metal–oxide–semiconductor) phase lock loop (PLL) chips with self-healing/self-calibration capabilities, allowing them to adapt, on the fly, to changes in temperature and other environment parameters. All CMOS PLLs typically have three major settings that self-healing and calibration can adjust: VCO (voltage controlled oscillator) coarse tuning, divider tuning, and CML (current mode logic) tuning. Previous work done at UCLA uses these “knobs” or settings exclusively to self-lock a PLL. Locking criteria is established by monitoring the control voltage with an analog-to-digital converter (ADC) to see if the PLL loop is settled in the middle of the range (locked), or sitting at the ground or supply (unlocked).